The present invention relates generally to reliability testing of semiconductor integrated circuit materials, and more specifically to advanced processes for reliability testing of low dielectric constant interlayer dielectric (ILD) materials.
To reduce qualification times for production products, the semiconductor industry relies heavily on time dependent, thermally accelerated stress and failure testing techniques to test new materials and new semiconductor structures. As these structures become ever smaller and the features ever thinner, as the devices are increasingly made of ever more exotic combinations of conductor and insulator materials, and as times-to-market get ever shorter and shorter, such thermally accelerated testing techniques are not only valuable, but in fact they have become essential.
Advances in the art of semiconductor processing have dramatically increased the number of functional elements on a semiconductor chip. This has been accomplished in some cases by increasing the size of the chip, but more often and more importantly by reducing the size of the minimum features on the chip. Where a one-micron design rule was once considered a challenge, sizes a full order of magnitude smaller are now typical, and the trend is continuing. The dielectric layers that separate and insulate these features from one another are similarly being scaled down in thickness and lateral dimension. Additionally, with the advent of newer materials, copper/interlayer dielectric integrated systems are increasingly required to reduce resistance/capacitance (RC) delay. The thinness and close proximity of these layers further require that they be made of low dielectric constant (low-k) dielectric materials having dielectric constants well under 3.9. The physical characteristics of these materials make the qualification of such copper/low dielectric constant interlayer dielectric integrated systems and the prediction of their lifetime reliabilities extremely important.
Improvements in processing have also made dielectric layer lifetimes increase, which increases the time and sample sizes needed to test and qualify new processes and materials. This conflicts with the continuing need to reduce design cycle times due to ever-increasing competition in the semiconductor industry. Accelerated stress testing is therefore critical in reducing the time to observe failures, with elevated temperatures being employed as a principle factor in accelerating the failure of a specific target fraction of the test population. Many chemical and physical processes leading to failure are accelerated by temperature in ways that can be readily modeled and reproduced in known fashion.
Each incremental reduction in testing time requires a higher test temperature, which in turn places an increased burden on the entire accelerated failure testing process. Low-k interlayer dielectric (ILD) materials, for example, are a critical component for the modem high-speed microprocessor.
It has been found that the conventional thermal stress for reliability tests cannot in general be directly applied to low-k ILD materials for reliability experiments at contemporary testing temperatures (e.g., T greater than 300xc2x0 C.). For example, SiLK (TM of Dow Chemical Co.) ILD and copper conductor combinations will be damaged at 350xc2x0 C. in air.
Thus, whereas conventional dielectric materials and test circuit structures are routinely tested on equipment using a standard test fixture, it was discovered that this same equipment could not be used for low-k dielectric materials because the low-k materials were unexpectedly vaporized or otherwise damaged by oxidation during the accelerated life tests at above their thermal threshold temperatures (TTT). This was believed to be due to the nature of porosity and low mechanical modulus of such materials, which could cause minute electrical concentrations that would cause small-scale or large-scale vaporizations and oxidations.
A solution to this problem has been long sought, but has long eluded those skilled in the art.
The present invention provides a testing system and method of operation therefor including a test fixture for electrical testing above interlayer dielectric thermal threshold temperatures (TTT) having an integrated-circuit-sized enclosed volume. The test fixture has an electrical connection from the enclosed volume to the outside thereof and a removable lid for sealing the enclosed volume in the test fixture. This allows testing equipment to be used for low-k dielectric materials without having the low-k materials unexpectedly vaporized or otherwise oxidized during accelerated life tests at above TTT, e.g., for SiLK low-k ILD, 300xc2x0 C.
Certain embodiments of the invention have other advantages in addition to or in place of those mentioned above. The advantages will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings.